Provides access to information about system and configuration.
More...
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| enum class | ogdf::CPUFeature { ogdf::CPUFeature::MMX
, ogdf::CPUFeature::SSE
, ogdf::CPUFeature::SSE2
, ogdf::CPUFeature::SSE3
, ogdf::CPUFeature::SSSE3
, ogdf::CPUFeature::SSE4_1
, ogdf::CPUFeature::SSE4_2
, ogdf::CPUFeature::VMX
, ogdf::CPUFeature::SMX
, ogdf::CPUFeature::EST
, ogdf::CPUFeature::MONITOR
} |
| | Special features supported by a x86/x64 CPU. More...
|
| |
| enum class | ogdf::CPUFeatureMask : unsigned int { ogdf::CPUFeatureMask::MMX = 1 << static_cast<int>(CPUFeature::MMX)
, ogdf::CPUFeatureMask::SSE = 1 << static_cast<int>(CPUFeature::SSE)
, ogdf::CPUFeatureMask::SSE2 = 1 << static_cast<int>(CPUFeature::SSE2)
, ogdf::CPUFeatureMask::SSE3 = 1 << static_cast<int>(CPUFeature::SSE3)
, ogdf::CPUFeatureMask::SSSE3 = 1 << static_cast<int>(CPUFeature::SSSE3)
, ogdf::CPUFeatureMask::SSE4_1 = 1 << static_cast<int>(CPUFeature::SSE4_1)
, ogdf::CPUFeatureMask::SSE4_2 = 1 << static_cast<int>(CPUFeature::SSE4_2)
, ogdf::CPUFeatureMask::VMX = 1 << static_cast<int>(CPUFeature::VMX)
, ogdf::CPUFeatureMask::SMX = 1 << static_cast<int>(CPUFeature::SMX)
, ogdf::CPUFeatureMask::EST = 1 << static_cast<int>(CPUFeature::EST)
, ogdf::CPUFeatureMask::MONITOR = 1 << static_cast<int>(CPUFeature::MONITOR)
} |
| | Bit mask for CPU features. More...
|
| |
Provides access to information about system and configuration.
◆ CPUFeature
Special features supported by a x86/x64 CPU.
This enumeration is used to specify spcial additional features that are supported by the CPU, in particular extended instruction sets such as SSE.
| Enumerator |
|---|
| MMX | Intel MMX Technology.
|
| SSE | Streaming SIMD Extensions (SSE)
|
| SSE2 | Streaming SIMD Extensions 2 (SSE2)
|
| SSE3 | Streaming SIMD Extensions 3 (SSE3)
|
| SSSE3 | Supplemental Streaming SIMD Extensions 3 (SSSE3)
|
| SSE4_1 | Streaming SIMD Extensions 4.1 (SSE4.1)
|
| SSE4_2 | Streaming SIMD Extensions 4.2 (SSE4.2)
|
| VMX | Virtual Machine Extensions.
|
| SMX | Safer Mode Extensions.
|
| EST | Enhanced Intel SpeedStep Technology.
|
| MONITOR | Processor supports MONITOR/MWAIT instructions.
|
Definition at line 78 of file System.h.
◆ CPUFeatureMask
Bit mask for CPU features.
| Enumerator |
|---|
| MMX | Intel MMX Technology.
|
| SSE | Streaming SIMD Extensions (SSE)
|
| SSE2 | Streaming SIMD Extensions 2 (SSE2)
|
| SSE3 | Streaming SIMD Extensions 3 (SSE3)
|
| SSSE3 | Supplemental Streaming SIMD Extensions 3 (SSSE3)
|
| SSE4_1 | Streaming SIMD Extensions 4.1 (SSE4.1)
|
| SSE4_2 | Streaming SIMD Extensions 4.2 (SSE4.2)
|
| VMX | Virtual Machine Extensions.
|
| SMX | Safer Mode Extensions.
|
| EST | Enhanced Intel SpeedStep Technology.
|
| MONITOR | Processor supports MONITOR/MWAIT instructions.
|
Definition at line 96 of file System.h.